Verilog HDL 综合要点[1] - mux结构及条件补全

作者:admin 日期:2010-06-19

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1. 如果case语句或者if - else - if语句中的条件语句不是互为唯一的，那么该语句将被综合为优先级结构；如果条件语句唯一，则被综合为mux结构。
//综合为优先级结构
always @(data) begin
    casex(data)
        8'b1xxx_xxxx : code = 7;
        8'b01xx_xxxx : code = 6;
        8'b001x_xxxx : code = 5;
        8'b0001_xxxx : code = 4;
        8'b0000_1xxx : code = 3;
        8'b0000_01xx : code = 2;
        8'b0000_001x : code = 1;
        8'b0000_0001 : code = 0;
        default         : code = 3'bx;
    endcase
end
//综合为mux结构
always @(data) begin
    case(data)
        8'b0000_0001: code = 0;
        8'b0000_0010: code = 1;
        8'b0000_0100: code = 2;
        8'b0000_1000: code = 3;
        8'b0001_0000: code = 4;
        8'b0010_0000: code = 5;
        8'b0100_0000: code = 6;
        8'b1000_0000: code = 7;
        default: code = 3'bx;
    endcase
end

2. 如果case或if - else - if 语句中语句是完整的，也就是各种条件可能都出现了，则不需要综合出锁存器。如果确实有条件是无关紧要的，或是根本不可能出现的，通过使用带任意值的default语句或else语句补全，可以缩减实现的器件尺寸
//完全不会产生锁存的设计
always @(data_3 or data_2 or data_1 or data_0 or select) begin

    case (select)
        0: mux_in = data_3;
        1: mux_in = data_2;
        2: mux_in = data_1;
        3: mux_in = data_0;
        default: mux_in = 32'bx;
    endcase
end
//这样也不会产生锁存，因为default语句补全了case语句
always @(data_3 or data_2 or data_1 or data_0 or select) begin

    case (select)
        0: mux_in = data_3;
        1: mux_in = data_2;
        2: mux_in = data_1;
        //3: mux_in = data_0;
        default: mux_in = 32'bx;
    endcase
end
//这样需要锁存
always @(data_3 or data_2 or data_1 or data_0 or select) begin

    case (select)
        0: mux_in = data_3;
        1: mux_in = data_2;
        2: mux_in = data_1;
        //3: mux_in = data_0;
        //default: mux_in = 32'bx;
    endcase
end

[本日志由 admin 于 2010-06-24 04:29 PM 编辑]